1. Field
Example embodiments relate to a method of forming an alignment key having a capping layer without additional processes, and a method of fabricating a semiconductor device including the alignment key having a capping layer.
2. Description of the Related Art
As semiconductor devices become dense and highly integrated, the design rule may be scaled down, and unit elements may become much smaller. Therefore, accurate alignment may be required between a semiconductor substrate and a mask during fabrication. Normally, alignment keys may be formed in a scribe lane of a semiconductor substrate for aligning the semiconductor substrate and the mask. One of the alignment keys may be formed in a scribe lane concurrently with an isolation layer for confining an active region of a chip region through a shallow trench isolation (STI) process and/or the like, and may have a shape which protrudes above the substrate. The alignment key may be used in a gate formation process, an ion implantation process, a silicidation blocking layer (SBL) for a selective silicide formation process, a contact formation process, and/or the like.
Because a power device, for example, an LCD driver IC (LDI) and/or the like, requires lower voltage operation for driving a logic circuit, and higher voltage operation for driving LCD operation, a dual gate oxide layer must be employed. A conventional method of forming the dual gate oxide layer may include forming an isolation layer confining an active region in a chip region of a semiconductor substrate, and concurrently forming a protruding alignment key in a scribe lane. After a first thermal oxide layer is formed on the substrate, the first thermal oxide layer may be wet-etched except for in a higher voltage region of the chip region, thereby forming a first gate oxide layer for a higher voltage operation. A second thermal oxide layer may be formed on the substrate, thereby forming a gate oxide layer for a lower voltage operation in a lower voltage region. A first gate oxide layer may be formed of a thick first thermal oxide layer in the higher voltage region, and a second gate oxide layer may be formed of a thin second thermal oxide layer in the lower voltage region.
However, because the conventional method of forming a dual gate oxide layer may include removing the first thermal oxide layer of the lower voltage region using a wet etch process, in order to remove a portion of the oxide layer of the alignment key, the step height difference between the substrate surface and the alignment key may be reduced. After the alignment key is formed, and when a subsequent wet etch process is performed, the oxide layer of the alignment key may be worn down. If the wearing-down of the oxide layer is substantial, because the step height difference of the alignment key may be removed during repeated wet etch processes, the alignment key may become level with the substrate surface. If the step height difference of the alignment key is removed, alignment may not be made precisely during subsequent processes, and misalignment may occur.
FIGS. 1A-1F illustrate a conventional method of forming an alignment key of a semiconductor device. Referring to FIG. 1A, a pad oxide layer 110 and a hard mask layer 120 may be formed on a semiconductor substrate 100. The hard mask layer 120 and the pad oxide layer 110 may be etched using photolithography and/or the like, to expose a portion of the semiconductor substrate 100 in a chip region 101, and a portion of the semiconductor substrate 100 in a scribe lane 105. The exposed semiconductor substrate 100 may be etched, thereby forming a first trench 131 in the chip region 101, and a second trench 135 in the scribe lane 105.
Referring to FIG. 1B, an oxide layer 140 may be formed on the hard mask layer 120 to fill the first trench 131 and the second trench 135. Referring to FIG. 1C, the oxide layer 140 may be etched using chemical mechanical polishing (CMP) and/or the like to planarize the surface of the substrate. Thus, a first isolation layer 141 may be formed inside the first trench 131, and a second isolation layer 145 may be formed inside the second trench 135. The first isolation layer 141 may confine an active region of the chip region 101.
Referring to FIG. 1D, the hard mask layer 120 and the pad oxide layer 110 may be removed. Referring to FIG. 1E, a photosensitive layer 150 may be deposited on the substrate, and patterned, to expose the second isolation layer 145 of the scribe lane 105. Referring to FIG. 1F, the exposed second isolation layer 145 may be etched using the photosensitive layer 150 as a mask, thereby forming an alignment key 135a. The alignment key 135a may have a recessed structure having a step height difference of H1 with respect to a substrate surface. The second isolation layer 145 may be completely etched, and the alignment key 135a may have a step height difference corresponding to the depth of the second trench 135.
Because the conventional alignment key 135a is recessed to have a step height difference below the substrate surface, the step height difference may be only increased when the oxide layer of the isolation layer 145 may be worn down during a subsequent wet etch process. Therefore, the aforementioned problems of the reduced step height difference of the alignment key 135a may be avoided, but the process may be complicated because an additional mask formation process may be needed to form the recessed alignment key 135a. 